1. FIELD OF THE INVENTION
This invention generally relates to data processing systems and more specifically to the alignment of data as it is interchanged between main memory and peripheral devices connected to input/output controllers in such a data processing system.
2. DISCUSSION OF THE PRIOR ART
A data processing system usually includes a central processing unit (CPU) which executes software instructions which are stored at addresses, or locations, in main memory. These software instructions are transferred to the CPU sequentially under the control of a program counter. The data that is processed is transferred into or out of the system by way of input/output devices, or peripheral devices, such as teletypewriters, magnetic disks, magnetic tapes, or line printers. Usually the data is temporarily stored in main memory before or after the processing by the central processing unit.
In a system having a plurality of peripheral devices coupled over a common bus, an orderly system must be provided by which bidirectional transfer of information may be provided between the main memory and such other peripheral devices. Usually such peripheral devices are coupled to the common bus by use of input/output controllers (IOCs) with a different type of IOC being provided for each type of peripheral device. In such systems the width of the unit of information interchanged between the peripheral device and its associated IOC may be different than the width of the unit of information which is normally read from or written into main memory. For example, in some cases a byte of information may be interchanged between the peripheral device and its associated IOC and a word of information consisting of multiple bytes of data may be read from or written into main memory. In these cases, apparatus must be provided to insure that the width of data being sent from the IOC to the main memory is acceptable to the main memory and to properly align it on the data lines of the common bus. In addition, logic must be provided to insure that information read from main memory is of a width acceptable to the IOC and is properly aligned on the common bus data lines in a position acceptable for receipt by the IOC.
Various methods and apparatus are known in the prior art for rationalizing the width of data as it is interchanged between the peripheral devices and the main memory and for aligning the data on the common bus so that it is acceptable to both the sender and receiver of the data. For example, a byte of data can be placed in a fixed position within the data lines by the I/O controller and the main memory can receive the data from the common bus and align it before it is stored in main memory. Similarly, when the information is being read from main memory, the main memory can read a multi byte word and extract the appropriate byte of data and place it in a fixed position on the data lines of the common bus before sending it to the peripheral device via the IOC. Alternatively, the IOC can, when reading data from a peripheral device, accumulate multiple bytes to form a word and transfer the full word to the main memory on the common bus data lines or it can properly position a single byte of data on the data lines and indicate to the main memory the position of the data byte. When information is being read from main memory to be output to a peripheral device, the main memory can deliver a multi byte word to the IOC and the IOC can then extract the desired byte of information and properly align it before transferring it to the peripheral device.
The above and similar schemes have the disadvantage that, if the main memory is composed of multiple units, each unit must have the ability to align data as it is received or sent to the peripheral device via an IOC. Similarly, if the data alignment is done within the I/O controllers, each I/O controller in a system containing a plurality of IOCs must have the byte alignment apparatus.